1. Field of the Invention
The present invention relates to a semiconductor memory device and a memory system employing the same, and more particularly to a semiconductor memory device connected to a memory controller and a memory system employing the same.
2. Description of the Background Art
Conventionally, a memory system employing a Synclink Dynamic Random Access Memory (hereinafter referred to as an SLDRAM) has been developed. This memory system, having a plurality of SLDRAMs connected in parallel corresponding to a memory controller, sequentially transfers data in synchronization with a clock signal. Therefore a high speed data transfer is allowed.
Japanese Patent Laying-Open No. 9-293393 discloses a technique for repairing (utilizing without discarding) a memory system when a defective SLDRAM is found after memory system completion. According to this technique, a built in test circuit, provided with each SLDRAM, tests a corresponding SLDRAM at system initialization to determine whether the SLDRAM is normal or not and transfers a test result to the memory controller. Hence, an ID value is not given to a defective SLDRAM and the memory controller is prevented from accessing to a defective SLDRAM, whereby system malfunction is prevented.
In a conventional technique, however, memory system performance is significantly deteriorated by an existence of even a single defective bit in an SLDRAM. An access to an SLDRAM is inhibited if one defective bit exists in the SLDRAM, that is, one defective bit in an SLDRAM means a loss of entire memory capacity of the SLDRAM from the memory system capacity.